1. Field of the Invention
The present invention relates to macrocells for data processing circuits. For the purpose of the present application, the term "macrocell" refers to any physically or logically modular component for a data processing circuit, for example a raw processor core, a cache, a memory management unit (MMU), or even a processor with cache and MMU, etc.
2. Description of the Prior Art
Typically, a data processing circuit such as a chip will include a number of macrocells that are arranged to interact with each other to perform data processing operations. Modular components such as the central processing unit, or processor core, used to apply instructions to data items read from memory, one or more caches or memories used to store instructions and data, a DMA bus master used to control activities such as data transfer, and an external memory interface for holding data to be output from the chip to memory, are examples of components which may be formed as macrocells.
During operation of the data processing circuit, the various macrocells will often interact with one another, for example by passing data, address information, or control information from one macrocell to another. To enable this transfer of information between the various macrocells, one or more buses are typically provided on the data processing circuit to connect the macrocells to one another. Since there is the potential for different macrocells to simultaneously seek to output data on to a particular bus, then bus arbitration logic is typically provided to control the various macrocells' access to the buses with the aim of removing any such conflict between the various macrocells.
In designing buses for data processing circuits, various different types of bus technology have been developed. Generally, these different types of bus fall into two categories, the first category being the bidirectional, or shared-driver, bus where the same bus is used to output data from a macrocell and also to receive data at that macrocell, whilst the second category is the unidirectional bus where one bus is provided for data being output from a particular macrocell, and a second, distinct bus is provided for data being input to that macrocell.
In data processing circuits that employ unidirectional buses, the various macrocells are typically arranged to always output a logic "0" or a logic "1" value, with multiplexer circuitry being provided to switch the output from any particular macrocell onto the output bus. However, in data processing circuits employing a bidirectional bus design, the outputs from each macrocell are typically not always driven, and when not outputting data, the macrocells are arranged to have a high impedance at their output, thereby removing the need for separate multiplexer circuitry to be provided.
Given the above two general categories of buses, it is clear that when designing a macrocell for a data processing circuit, it is important to know which type of bus the macrocell is intended to be connected to, since this will affect the design of the macrocell interface to the bus. However, this adds to design cost, and limits the reusability of macrocells.
Hence, it is an object of the present invention to provide a macrocell which can be used with either unidirectional or bidirectional buses.